Copper damascene processes are incompatible with some aspects of industry standard aluminum-based design layouts. Specifically, wide metal wires, wide regions devoid of metal wires (i.e., “whitespace”), local regions of high metal-pattern-density, and local regions of low metal-pattern-density are all incompatible with state of the art in copper damascene processing. Consequently, the interconnect levels of semiconductor designs must be redrawn in order to accommodate the aforementioned limitations of damascene copper, specifically by following maximum-linewidth rules, wide-line/wide-space rules, and local metal-pattern-density rules. These constraints on interconnect layouts are a significant obstacle to the utilization of damascene copper processes.
The related art generally uses one of two methods to produce a connection between areas of high via concentration (i.e., “via farms”) and copper damascene layers in a semiconductor device. These two methods differ in their respective approaches to existing via farms. The first method does not allow any via farms, while the second method rebuilds most or all of the via farms.
In the first method, via farms are not allowed. Instead, only a single row of vias is allowed around the perimeter of the intersection of wide metal wires. This approach requires that industry-standardized designs be manually adjusted to remove “farm” vias, and subsequently retimed because the total via resistance for a large farm can be much less than the total via resistance for a single ring of vias along the perimeter.
The second method requires the rebuilding of all via farms. A design tool may be applied to the semiconductor device design. The design tool, such as those known in the art, may identify intersections of wide metal connected by vias, remove all vias from the intersection, and replace the vias in a preferred configuration (e.g., a single or double row at the perimeter of the intersection). However, there are two major drawbacks with this method. First, a large proportion of the via shapes are removed from any large via farm. Second, the design data is altered. Removing and replacing a large number of via shapes can have an unpredictable effect, both on the run-time, and on the results of subsequent verification procedures such as Design Rule Checking (DRC) and Layout Versus Schematic (LVS) checking.